1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device for use as an ultraviolet erasable programmable read-only memory (EPROM) or an electrically erasable programmable read-only memory (EEPROM).
2. Description of the Related Art
Nonvolatile semiconductor memory devices such as an EPROM and an EEPROM have an array of memory cells each including a floating gate electrode on a gate insulating film of a MOS transistor and a control gate electrode disposed on the floating gate electrode with a thin insulating layer interposed therebetween. Generally, those memory cells which belong to one column have drain and source regions formed as an integral structure, and those memory cells which belong to one row have control gate electrodes formed as an integral structure serving as a word line. Japanese patent publication No. 56-40505 (JP, B2, 56-40505), for example, discloses a typical programmable semiconductor memory device.
FIG. 1 schematically shows in plan a conventional semiconductor memory device.
As shown in FIG. 1, an element-isolating insulating film 52 is disposed on the surface of a semiconductor substrate 51 of silicon in surrounding relation to a memory cell region 62. The memory cell region 62 contains three rows and four columns of memory cells. Source regions 55 and drain regions 56 extend vertically in FIG. 1 and are alternately arranged horizontally at given intervals or isolation intervals L. Control gate electrodes 59 in the respective rows extend horizontally in FIG. 1, each of the control gate electrodes 59 having a width W. Floating gate electrodes 64 are disposed between the source and drain regions 55, 56 and below the respective control gate electrodes 59. Each of the floating gate electrodes 64 has a size W.times.L. In each of the memory cells, the channel length is equal to the isolation interval L, and the channel width is equal to the width W of the control gate electrodes 59. To isolate the source and drain regions 55, 56 completely from each other in areas where no control gate electrodes 59 are present, a first interlayer insulating film 57 is disposed which fills recesses between the floating gate electrodes 64.
To manufacture the conventional semiconductor memory device, a layer 64' which will serve as the floating gate electrodes is formed between the source regions 55 and the drain regions 56 so as to extend along columns across a plurality of memory cells. Then, a first interlayer insulating film 57 is formed, followed by the formation of control gate electrodes 59, whereupon the layer 64' is separated in self-alignment into floating gate electrodes 64 of the respective memory cells.
However, the conventional semiconductor memory device, described above, suffers the following problems because the width of the floating gate electrodes, i.e., the channel length of the memory cells, is equal to the element-isolation interval between the source and the drain:
(a) When data are to be written in a memory cell with channel hot electrons, a write current that is required to write tile data is large, resulting in a large power consumption. For example, a write current is 500 .mu.A if the channel length L is 0.6 .mu.m and the channel width W is 1.2 .mu.m.
(b) Inasmuch as the channel length of a memory cell transistor is equal to the isolation interval, it is impossible to freely select only the channel length. For example, even if a length of 0.5 .mu.m is optimum as the channel length of a memory cell transistor, since a current leakage occurs between adjacent source and drain regions across the length of 0.5 .mu.m, this optimum length cannot be used as the channel length. As a result, a limitation is imposed on the selection of the channel length.